1. Field of the Invention
The present invention relates to a semiconductor memory device having an SRAM cell which stores data by two pairs of inverters.
2. Description of Related Art
An SRAM (Static Random Access Memory) is widely used as a multi-purpose memory and a mixed logic memory.
FIG. 23 shows a circuit diagram depicting an SRAM cell in a six transistor configuration having a P-channel MOS transistor (hereinafter, called PMOS) as a load.
The memory cell 100 has two load transistors P1 and P2 formed of a PMOS transistor, two driver transistors N1 and N2 formed of an N-channel MOS transistor (NMOS), and two transfer transistors N3 and N4 formed of an NMOS transistor.
Between a power supply node NDdd in the cell to which power is supplied from a supply line of a power supply voltage Vdd (hereinafter, a Vdd supply line 4) and a supply line 2 at reference voltage (for example, ground voltage), the load transistor Pi is vertically connected to the driver transistor N1, and the load transistor P2 is vertically connected to the driver transistor N2.
The gates of the load transistor P2 and the driver transistor N2 are together connected to the connecting point of the load transistor Pi to the driver transistor N1 to form a storage node ND1. Similarly, the gates of the load transistor Pi and the driver transistor N1 are together connected to the connecting point of the load transistor P2 to the driver transistor N2 to form a storage node ND2.
One of the source and the drain of a transfer transistor N3 is connected to the storage node ND1, and the other is connected to a bit line BL, and the gate is connected to a word line WL. Similarly, one of the source and the drain of a transfer transistor N4 is connected to the storage node ND2, the other is connected to a bit complementary line BL_, and the gate is connected to the word line WL.
This SRAM 100 in the six transistor configuration has high compatibility with logic process, and can be operated at high speed. However, the SRAM has disadvantages that operating electric power and standby electric power are great.
As one scheme of solving the disadvantages, there is a scheme that the voltage supplied to the SRAM is controlled.
As one example, there is a scheme in which an SRAM cell is driven at high voltage when it is necessary to operate the SRAM at high speed, whereas the SRAM is driven at low voltage when it is operated at low speed, or it is in standby, whereby power consumption is suppressed.
However, when the SRAM is driven at low voltage, an SNM (Static Noise Margin) indicating the stability of the SRAM becomes small, and particularly, a problem arises that data is written wrong in read operation. Hereinafter, the relation between the operating voltage and the SNM will be described.
FIG. 24A shows a single inverter in the SRAM cell 100.
Here, for the sake of simplification, the load is replaced by a resister. A load resister R and an NMOS transistor NT (the driver transistor N1 or N2) are vertically connected between the power supply voltage Vdd and the ground voltage, and an output voltage Vout is taken out of the connecting point. An input voltage Vin is applied to the gate of the NMOS transistor NT.
Two pairs of the inverters like this are arranged in the cell, in which the inverters are connected to each other so that one of the input voltage Vin of the pairs is the output voltage Vout of the other pair and one of the output voltage Vout of the pairs is the input voltage Vin of the other pair (see FIG. 23). In addition, as shown in FIG. 23, the node of the output voltage Vout is connected to one of the pair of the bit lines BL and BL_ through the transfer transistor (N3 or N4 in FIG. 23).
FIG. 24B shows the input/output characteristics of the inverter. In the drawing, a solid line indicates a characteristic curve (first characteristic curve) 101 of a first inverter, and a broken line indicates a characteristic curve (second characteristic curve) 102 of a second inverter.
In the first characteristic curve 101, when the input voltage Vin is increased from zero, the NMOS transistor NT is first turned off, and the output voltage Vout maintains high level near the power supply voltage Vdd. However, when the NMOS transistor NT is started to turn on, the drain current Ids is carried through the load resister R. Thus, the output voltage Vout drops rapidly, and it is stabilized at low level that is decided by the value of the ON resistance of the NMOS transistor NT and the value of the load resister R.
Since the second inverter has the characteristics that the input and the output of the first inverter are inverted, the second characteristic curve is the curve as indicated by the broken line shown in FIG. 24B.
Since two intersection points of the first and the second characteristic curves 101 and 102 are the stable points for the operation, in the SRAM cell, the potential difference between the two intersection points is stored as binary information. The stable points (operating points P1 and P0) are determined as they satisfy the equation (Vdd−Vout)/R =Ids (Vout, Vin).
The difference between the input voltage VH at the operating point P1 and the input voltage VL at the operating point P0 is referred to as a logic amplitude ΔV. In addition, the input voltage difference between the intersection point P1 and the inflection point close thereto is represented by a static noise margin SNMH on the high level side, and the input voltage difference between the intersection point P0 and the inflection point close thereto is represented by a static noise margin SNML on the low level side.
The description above is the case of using the load resister R. FIG. 25 shows a characteristic diagram depicting the case in which the load resister R is replaced by the PMOS transistor and the power supply voltage Vdd is varied.
When the first characteristic curves 101 are compared with each other between FIG. 25 and FIG. 24B, the curve shown in FIG. 25 is more smoothly varied on the high level side of the input voltage Vin. This is because the load transistor functions as a variable resister. On the other hand, the curve is supposed to smoothly vary on the low level side of the input voltage Vin, but it is varied sharp because of the existence of the transfer transistor.
FIG. 25 shows a table depicting the static noise margin SMNL on the low level side when the power supply voltage Vdd is gradually decreased from 1.4 V to 0.6 V. In association with the decrease of the power supply voltage, the reduction in the static noise margin SNM is a factor of read error in particular.
As a scheme to cope with this disadvantage, a scheme is proposed in which two voltages are supplied to a memory cell (see K. Zhang, etc., “A 3-GHz 70 Mb SRAM in 65 nm CMOS Technology with integrated Column-Based Dynamic Power Supply,” ISSC 2005/SESSION 26/NON-VOLATILE MEMORY/26.1, p. 474 (Non-Patent Reference 1)).
As another scheme, a scheme is proposed in which the voltage of a memory cell is boosted in the memory operation of an SRAM (see Azeez J. Bhavnagarwala etc., “A Transistor CMOS SRAM with Single, Logic Vdd and Dynamic Power Rails”, VLSI Circuit 2004, P.292 (Non-Patent Reference 2)).
FIG. 26A shows a circuit diagram described in Non-Patent Reference 2, and FIG. 26B shows an illustration depicting the capacitive coupling of word lines.
In the circuit, a memory cell array is separated into small scale subarrays 110, and a circuit is arranged to boost word lines at every subarray. The booster circuit is provided with a pair of PMOSs 111 in which the gate is connected to each of word lines WL0 to WL2, and a supply line VDD of power supply voltage is connected to power lines PL0 to PL3 through each of the PMOSs 111. Here, attention is focused on the word line WL1. When a pulse 112 at high level rises, two PMOSs 111 having the gate thereof connected to the word line WL1 are turned off. Therefore, power supply to the power lines PL1 and PL2 at power supply voltage is stopped, the power lines PL1 and PL2 are boosted from the power supply voltage level to a higher level 113. As shown in FIG. 26B, this pressure rise occurs because each of the power lines PL1 and PL2 is capacitive coupled to the word line WL1 on the side wall (combined capacitance: Cc).
At this time, in all the SRAM cells connected to the word line WL1 in the subarray 110, the connecting point of the power lines PL1 and PL2 is boosted to the level 113 higher than the power supply voltage.
Thus, the read operation is accelerated.